USBHS=0, RNGA=0, USBHSPHY=0, FTM3=0, USBHSDCD=0, FTM2=0, SDHC=0, SPI2=0, ADC1=0, FLEXCAN1=0
System Clock Gating Control Register 3
| RNGA | RNGA Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| USBHS | USBHS Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| USBHSPHY | USBHS PHY Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| USBHSDCD | USBHS DCD Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| FLEXCAN1 | FlexCAN1 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| SPI2 | SPI2 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| SDHC | SDHC Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| FTM2 | FTM2 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| FTM3 | FTM3 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| ADC1 | ADC1 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |